1. Field of the invention
The present invention relates generally to a parallel in serial out (PISO) circuit for use in a digital data communication system, and more specifically to a PISO circuit which is suitable for use in a physical layer defined by IEEE (Institute of Electrical and Electronic Engineers) 1394 standard.
2. Description of Related Art
In order to comply with the demand for large volume transfer of digital data at a high speed between a personal computer and a peripheral(s) byway of example, the IEEE 1394-1995 Standard for a High Performance Serial Bus (hereinafter sometimes referred to as 1394 serial bus) was developed. As is known in the art, the 1394 serial bus protocols are described as a set of three stacked layers: transaction layer, link layer and physical layer. Explaining these layers in brief, the transaction layer defines a complete request-response control to perform the bus transactions. The link layer provides a one-way (half-duplex) data transfer with confirmation of request service to the transaction layer, and further provides addressing, data checking, and date framing for packet transmission and reception. On the other hand, the physical layer translates the logical symbols used by the link layer into electrical signals, and defines the mechanical interfaces for the serial bus. More specifically, the physical layer has three primary functions: transmission and reception of data bits, arbitration, and provision for the electrical and mechanical interface.
Before turning to the present invention, it is deemed preferable to briefly describe, with reference to FIGS. 1-6(C), prior art to which the present invention is applicable.
Referring to FIG. 1, a conventional data transfer circuit (denoted by 10) is schematically shown in block diagram form, which circuit is provided in the physical layer. As shown, the data transfer circuit 10 generally comprises a parallel in serial out (PISO) circuits 12 and 14, a clock frequency divider 16, a timing controller 18, and a data""strobe encoder 20, all of which are coupled as illustrated.
According to the IEEE 1394 protocol, the data transfer speed is selected among 400, 200 and 100 Mbps (Mega-bit per second). The cock frequency divider 16, which takes the form of 3-stage counter using three flip-flops (FFs), receives a 400 MHz clock, and divides the same so as to output three different clocks that have respectively clock rates of 200 MHz, 100 MHz, and 50 MHz. In addition, the clock frequency divider 16 allows the inputted 400 MHz clock to pass therethrough. That is to say, the clock frequency divider 16 issues the four different clocks of 400 MHz, 200 MHz, 100 MHz and 50 MHz, all of which are applied to the timing controller 18. These clocks are respectively denoted by CLK400, CLK200, CLK100, and CLK50 in the instant disclosure.
The data/strobe encoder 20 is supplied with a parallel data DATA_Parallel of 8 bits (in the instant case) to be transmitted in serial, and outputs two parallel data: one is a parallel data DATA_Parallel which is exactly the same as the inputted parallel data; and the other is a parallel strobe signal STRB_Parallel. These parallel data DATA_Parallel and STRB_Parallel are applied to each of the PISO circuits 12 and 14. Although not shown in FIG. 1, the parallel data (8 bits) are respectively numbered 0, 1, 2, . . . , 7 in order of sequential transmission from each of the PISO circuits 12 and 14. The parallel strobe signal STRB_Parallel is produced by simply reversing a logic level of each of the odd number data bits (viz., data bits respectively numbered 1, 3, 5, and 7) of the parallel data of DATA_Parallel.
As mentioned above, according to the IEEE 1394 standard, two serial data DATA_Serial (Tx) and STRB_Serial (Tx), which are respectively outputted from the PISO circuits 12 and 14, are transmitted at the transfer speed of 400, 200, or 100 Mbps using a lock rate of 400 MHz, 200 MHz, or 100 MHz. In order to select one of these clock rates, the timing controller 18 is supplied with data transfer speed control signals SPD0 and SPD1, and also receives the above-mentioned four clocks CLK400, CLK200, CLK100, and CLD50. The speed control signals SPD0 and SOD1 will further be described later.
Referring to FIG. 2, the timing controller 18 of FIG. 1 is shown in detail in block diagram form. As shown in FIG. 2, the timing controller 18 comprises decoders 22a-22c, flip-flops (FFs) 24a-24e, and selectors 26a-26c, all of which are coupled as shown. As mentioned above, the controller 18 is supplied with the four locks CLK400, CLK200, CLK100, and CLK50, and further receives the data transfer speed control signals SPD0 and SPD1 from logic circuitry (not shown) provided in the physical layer. The timing controller 18 per se is not directly concerned with the present invention, and hence, only the brief description thereof will be given for the sake of simplifying the instant disclosure. The decoder 22c receives the data transfer speed control signals SPD0 and SPD1, and issues data transfer speed control signals C1-C3. The control signal C1 is applied to the selectors 26a and 26c, while the control signals C2 and C3 are both applied to each of the selectors 26a and 26b. 
The timing controller 18 can be divided into two sections in terms of function thereof. That is, the first section includes the flip-flop 24e and the selectors 26b-26c, while the second section includes the decodes 22a-22b, the flip-flops 24a-24d, and the selector 26a. When both of the data transfer speed signals SPD0 and SPD1 is non-active, the output of the selector 26c of the first section becomes CLK400 (400 MHz), and the output of the flip-flop 24d is 50 MHz (viz., one eight of 400 MHz). Further, when only SPD1 becomes active, the output of the selector 26c is CLK200 (200 MHz) and at the same time, the output of the flip-flop 24d is 25 MHz. Still further, when only SPD0 becomes active, the output of the selector 26c becomes CLK100, and at the same time, the flip-flop 24d becomes 12.5 MHz. The clock and the data acquisition signal thus generated are both applied to the PISO circuits 12 and 14.
FIG. 3 is a diagram showing the PISO circuit 12 in detail. It is to be noted that the other PISO circuit 14 is configured in exactly the same manner as the PISO circuit 12. The PISO circuit 12 is a conventional type 8-bit shift register which is configured by eight flip-flops 30a-30h, selectors 32a-32g, and an AND gate 34. A clock signal (400 MHz, 200 MHz, or 100 MHz) is applied t the clock terminals of the flip-fops 30a-30h. Data bits D0-D6 are respectively applied to the selectors 32a-32g by way of input terminals T0-T6, and on the other hand, a data bit D7 is applied to the AND gate 34 via an input terminal T7. When the data acquisition signal DAS is applied to the PISO circuit 12, the flip-flops 30a-30h acquire respectively the outputs of the preceding circuits. The contents of the flip-flops 30a-30h are then shifted in synchronism with the clock until the data bit D7 is outputted from the flip-flop 30h, and thereafter, these operations are repeated on the following eight parallel data (viz., D8-D15).
FIG. 4 is a timing chart graphically showing the above-mentioned operation of the PISO circuit 12. It is clearly understood that the first 8-bit parallel data D0-D7 are acquired at the flip-flops 30a-30h at a time in response to the data acquisition signal DAS, after which the PISO circuit 12 outputs in series D0-D7 in synchronism with the clock as DATA_Serial (Tx), and thereafter, the same operation is carried out on the following 8-bit parallel data D8-D15.
FIG. 5 is a timing chart showing the operation of the other PISO circuit 14. As mentioned above, the parallel strobe data STRB_Parallel differs from the corresponding parallel data DATA_Parallel only with respect to the fact that the odd number data bits of DATA_Parallel (viz., data bits respectively number 1, 3, 5, . . . ) are reversed in terms of logic level. In FIG. 5, the character xe2x80x9cXxe2x80x9d attached to each of the data bits such as D1, D3, etc. denotes that the logic level of each of the data bits D1, D3, . . . etc. of DATA_Parallel is reversed. Accordingly, the timing chart of FIG. 5 is readily understood when referring to that of FIG. 4, and hence, further description of the timing chart of FIG. 5 will be omitted for the sake of simplifying the instant disclosure.
FIG. 6(A) is a timing chart schematically showing DATA_Serial (Tx) and STRB_Serial (Tx) which are respectively outputted from the. PISO circuits 12 and 14. As shown, the logic level of each of the data bits at the odd bit numbers 1, 3, 5, and 7 of STRB_Serial (Tx) are reversed with respect to the corresponding data bits of DATA_Serial (Tx).
FIG. 6(B) is a timing chart schematically showing a dock which is reproduced by performing exclusive-OR operation of DATA_Serial (Rx) and STRB_Serial (Rx) received at a given node (e.g., a certain periphery coupled to a personal computer (for example)). The reproduction of the clock using the received DATA_Serial (Rx) and STRB_Serial (Rx) is to improve the skew tolerance of data bits transferred across the serial bus.
The prior art thus far described has encountered the difficulty that the power consumption of the data transfer circuit 10 is undesirably high in that a large number of the flip-flops operable at the high frequency of 400 MHz are provided. In more specific terms, the clock frequency divider 16 is provided with three flip-flops operating at the 400 MHz clock, and further, the timing controller 18 requires the five flip-flops which are configured such as to operate at 400 MHz. Still further, each of the PISO circuits 12 and 14 contains eight flip-flops operable at 400 MHz. Summing up, there are 24 (twenty four) flip-flops in total in the data transfer circuit 10, each of which is operable at 400 MHz. Accordingly, if the circuit 10 operates such as to output DATA_Serial and STRB_Serial at 400 MHz, then the power consumption becomes objectionable when the circuit 10 is fabricated on a semiconductor chip.
One approach to overcoming the above-mentioned problem is disclosed in Japanese Laid-open Patent Application No 10-22837. According to this prior art, two selectors are provided for respectively converting 8-bit parallel data and 8-bit parallel strobe into the corresponding two 8-bit serial data. This prior art utilizes eight switches in place of eight flip-flops in a shift-register, wherein each switch is designed so as to operate at a high frequency, and as such, it is expected to reduce the overall power consumption of the data transfer circuit. However, the switches disclosed in the prior art in question are directly coupled at the outputs thereof, and thus die signals generated therefrom tend to be adversely affected by the existence of the output wire load and the output capacitance of each of the switches. Consequently, the rising and falling edges of each of the output pulses is apt to be deteriorated, leading to the fact that jitters are liable to occur in each of the received DATA_Serial (Rx) and STRB_Serial (Rx). The jitters in turn cause skews between DATA_Serial (Rx) and STRB_Serial (Rx), which renders it difficult to correctly reproduce the clock because the duty cycles of the pulses may be considerably different with each other as shown in FIG. 6(C).
It is therefore an object of the present invention to provide a PISO circuit via which the power consumption can effectively be realized while correctly reproducing a clock at a data receiving side (node).
In brief, the object is achieved by a parallel in serial out (PISO) circuit for converting inputted parallel data bits into a corresponding serial data is disclosed. In the case where the inputted parallel data bits is four, the PISO circuit comprises a first latch group, which is provided with four flip-flops, for latching respectively the four data bits at the four flip-fops in synchronism with a clock of 50 MHz. A first selector group is further provided which comprises two selectors each of which selectively receives two different data bits latched at the first latch group and each of which outputs sequentially the received two different data bits in synchronism with the clock of 50 MHz. A second latch group, which follows the first selector group, is provided with two flip-flops for latching the two data bits outputted from the two selectors of the first selector group in synchronism with a clock of 100 MHz. The PISO circuit further comprises a single selector for selectively receiving the two data bits latched at the second latch group in synchronism with the clock of 100 MHz. A flip-flop, which is preceded by the single selector, latches the data bit outputted from the single selector in synchronism with a clock of 200 MHz. Thus, the four data bits inputted in parallel to the PISO circuit is converted into the corresponding serial data.
One aspect of the present invention resides in a parallel in serial out circuit for converting 2r data bits (r is a natural number) applied thereto in parallel into a corresponding serial data, comprising: first to (r+1)-th latch means wherein the s-th (1xe2x89xa6sxe2x89xa6r+1) latch means comprises 2r+1xe2x88x92s flip-flops; first to r-th selector means respectively provided between adjacent two of the first to (r+1)-th latch means; wherein the t-th latch means (1xe2x89xa6txe2x89xa6r) is provided such as to latch 2r+1xe2x88x92t data bits in synchronism with a clock signal of 2txe2x88x922xc3x97100 MHz, and the (r+1)-th latch means is provided to latch a single data bit in synchronism with a clock signal of 2t+1xe2x88x922xc3x97100 MHz, and wherein the u-th selector means (1xe2x89xa6uxe2x89xa6r) is provided with 2rxe2x88x92u selectors each of which receives two different data bits outputted from the u-th latch means and generates sequentially the received two different data bits in synchronism with a clock signal of 2uxe2x88x922xc3x97100 MHz.
Another aspect of the present invention resides in a parallel in serial out circuit for converting four data bits applied thereto in parallel into a corresponding serial data, comprising: first latch means, which is provided with four flip-flops, for latching respectively the four data bits at the four flip-flops in synchronism with a clock of 50 MHz: first selector means comprising two selectors each of which selectively receives two different data bits latched at the first latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 50 MHz: second latch means, which is provided with two flip-flops, for latching the two data bits outputted from the two selectors of the first selector means in synchronism with a clock of 100 MHz; second selector means comprising a single selector for selectively receiving the two data bits latched at the second latch means in synchronism with the clock of 100 MHz; and a flip-flop for latching the data bit outputted from the single selector in synchronism with a clock of 200 MHz.
Still another aspect of the present invention resides in a parallel in serial out circuit for converting eight data bits applied thereto in parallel into a corresponding serial data, comprising: first latch means, which is provided with eight flip-flops, for latching respectively the eight data bits at the eight flip-flops in synchronism with a clock of 50 MHz; first selector means comprising four selectors each of which selectively receives two different data bits latched at the first latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 50 MHz; second latch means, which is provided with four flip-flops for latching respectively the four data bits outputted from the four selectors of the first selector means at the four flip-flops in synchronism with a clock of 100 MHz; second selector means comprising two selectors each of which selectively receives two different data bits latched at the second latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 100 MHz; third latch means, which is provided with two flip-flops, for latching respectively the two data bits outputted from the two selectors of the second selector means in synchronism with a clock of 200 MHz; third selector means comprising a single selector for selectively receiving two different data bits latched at the third latch means in synchronism with the clock of 200 MHz and a flip-flop for latching the data bit outputted from the single selector in synchronism with a clock of 400 MHz.
Still another aspect of the present invention resides in a parallel in serial out circuit for converting sixteen data bits applied thereto in parallel into a corresponding serial data, comprising: first latch means, which is provided with sixteen flip-flops, for latching respectively the sixteen data bits at the sixteen flip-flops in synchronism with a clock of 50 MHz; first selector means comprising eight selectors each of which selectively receives two different data bits latched at the first latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 50 MHz second latch means, which is provided with eight flip-flops, for respectively latching the eight data bits outputted from the eight selectors of the first selector means at the eight flip-flops in synchronism with a clock of 100 MHz; second selector means comprising four selectors each of which selectively receives two different data bits latched at the second latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 100 MHz; third latch means, which is provided with four flip-flops, for latching respectively the four data bits outputted from the four selectors of the second selector means at the four flip-flops in synchronism with a clock of 200 MHz third selector means comprising two selectors each of which selectively receives two different data bits latched at the third latch means and each of which outputs sequentially the received two different data bits in synchronism with the clock of 200 MHz; fourth latch means, which is provided with two flip-flops for latching respectively the two data bits outputted from the two selectors of the third selector means in synchronism with a clock of 400 MHz; fourth selector means comprising a single selector for selectively receiving two different data bits latched at the fourth latch means in synchronism with the clock of 400 MHz; and a flip-flop for latching the data bit outputted from the single selector in synchronism with a clock of 800 MHz